The present invention relates generally to semiconductor device processing and, more particularly, to methods for processing array and support areas of a vertical DRAM cell device.
The manufacture and design of integrated circuits has greatly increased in sophistication in recent years, particularly in regard to the increase of integration density. Increased integration density leads to economic advantages as increased numbers of devices and circuits may be placed on a single chip and/or within a single package (which may include a plurality of chips). Performance improvements such as reduced signal propagation time and noise immunity can usually be achieved as integration density is increased due to reduction in length of signal paths, capacitance between connections and the like. This performance gain is particularly important in integrated circuits.
Integrated circuits such as dynamic random access memories (DRAMs) can have millions of similar devices on a single chip (often collectively referred to as an array or array portion of the chip design) which are controlled throughout the chip or partitions thereof by circuits such as addressing circuits, sense amplifiers and the like, generally referred to as support circuits. Unfortunately, the circuit requirements are generally different for the array and support regions of the chip, and ideally would require different processes during manufacture. For example, junctions with self-aligned silicides (salicides) are desired in the support regions to minimize series resistance. On the other hand, shallow junctions with low dose implants and no silicides are desired in the array in order to minimize junction leakage.
As another example, during conventional processing of the array, an array top oxide is deposited and certain portions are thereafter removed. Generally, the top oxide is removed entirely from the support area. (See, for example, R. Divakaruni et al. xe2x80x9cIn ULSI Process Integration IIxe2x80x9d, Electrochemical Society Proceeding Vol. [2001]-2) However, existing wet etch processes may cause shallow trench isolation (STI) areas within the support area to be exposed to overetching thereof which, in turn, may lead to voids at the trench edges, gate shorts and the like.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for processing a semiconductor memory device, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area or the initial nitride layer added helps to protect the support area from chemical mechanical polish or wet etch processes respectively implemented during the formation of active device areas within the array area.
In a preferred embodiment, the method includes forming a first cap oxide over the support area, the first cap oxide preventing the removal of the initial pad nitride material contained within the support area during the removal of the initial pad nitride material contained within the array area. Following the formation of active device areas within the array area, a cap nitride is formed over the array area. A second cap oxide is formed over the cap nitride, and the initial pad nitride material contained within the support area is removed. The second cap oxide prevents the removal of the cap nitride formed over the array area.